Get An Artificial Intelligence Approach to VLSI Routing PDF
By R. Joobbani
Routing of VLSI chips is a crucial, time eating, and hard challenge. the trouble of the matter is attributed to the massive variety of usually conflicting elements that impact the routing caliber. conventional strategies have approached routing by way of ignoring a few of these elements and implementing pointless constraints with a view to make routing tractable. as well as the imposition of those regulations, which simplify the issues to some extent yet even as decrease the routing caliber, conventional techniques use brute strength. they generally rework the matter into mathematical or graph difficulties and entirely forget about the explicit wisdom in regards to the routing activity that could vastly aid the answer. This thesis overcomes many of the above difficulties and offers a process that plays routing just about what human designers do. In different phrases it seriously capitalizes at the wisdom of human services during this quarter, it doesn't impose pointless constraints, it considers the entire various factors that have an effect on the routing caliber, and most significantly it permits consistent consumer interplay during the routing technique. to accomplish the above, this thesis provides heritage approximately a few consultant strategies for routing and summarizes their features. It then experiences intimately different elements (such as minimal zone, variety of vias, cord size, etc.) that impact the routing caliber, and the various standards (such as vertical/horizontal constraint graph, merging, minimum rectilinear Steiner tree, etc.) that may be used to optimize those factors.
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Extra resources for An Artificial Intelligence Approach to VLSI Routing
They do not allow pre-routed nets. Critical nets such as power; ground and clocks require the shortest possible path. The best way to assure the shortest length of wire is to pre-route the critical nets manually and then allow the router to 19 route the rest of the routing. Very few algorithms [Hamachi 84] allow pre-routed nets or for that matter any obstacle in the routing area. 6. They do not allow user interaction throughout the routing process. Less than 100% routing means human designers have to manually route the un routed nets often involving the rerouting of some of the previously routed nets.
Figure 3·9 shows an example of a channel, a net with 11 pins and the distance between consecutive pins. Table 3·3 shows the step by step calculation of the optimal RST of the channel of Figure 3·9. The desired MRST is shown in Figure 3·10. Aho, et. al. [Aho 77] prove that the above algorithm can be implemented to construct an optimal RST for A in O(n) computational steps. al a2 11" ·"I bl b2 14 a3 35 b3 a5 +·1 . "I b4 b5 a6 a7 a8 ,9 b7 b8 b9 37 b6 Figu re 3-9: A channel with a net and the distances between pins of the net.
7 LI (J (i l. o 15 14 •• 1- ••••••••••••• 13 •• 1-' •••••••••••• 1'J ...... :~ J .. 1- •••••••• ••••• 1- •••••••••••••••••••••• .. ~ ...... l ..... 1 18 0 ••••• Ifi 3 19 0 --r 20 18 20 •• •• •• •• •• r- • . 17 4 7. 24 ••••• t- ................... 16 1 • •• •• •• 9 12 ;'0 •• •• •• •• r •••••••••• 14 24 Z1 (J . 1. 1.. .. .. 1- ••••••• .......... 10 • -I- •••• •• 3 • -t-. -t- ................ 24 17 16 23 • •• • • • • • •• • • • 4 7 6 III •• 5 22 •• 9 2 8 0 18 9 12 15 24 15 10 23 o 0 22 18 0 Figure 2·14: An example attempted by Hierarchical wire routing.
An Artificial Intelligence Approach to VLSI Routing by R. Joobbani